Digital modulation schemes are becoming the standard method of carrying information in communications systems. They allow for better utilization of frequency spectrum, carry higher data rate information, have better performance and offer easier integration with digital processing systems. Examples of such modulation schemes include M-ary Frequency Shift Keying (MFSK), and Minimum Shift Keying (MSK). When M=2, MFSK is referred to as binary Frequency Shift Keying (FSK). FSK and MSK are well used digital modulation schemes due to their easy implementation. Typically, they are employed for low to medium data rate systems, i.e., 128 kbps.
Implementations of FSK modulators are common and there are various ways to implement an FSK modulator. One way is to use the baseband information bits (to be transmitted) to directly shift the frequency of a Voltage-Controlled-Oscillator (VCO) as shown in FIG. 1. The FSK modulator 10 of FIG. 1 includes a filter 12 for filtering baseband data, and a VCO 14. In the FSK modulator 10, a binary “0” corresponds to a frequency shift above the nominal VCO frequency, while a binary “1” corresponds to a frequency shift below the nominal VCO frequency. To avoid instantaneous change in the VCO frequency, the baseband data is filtered by typically a low pass filter (12 of FIG. 1), i.e., Gaussian filter, to smooth the transitions of the square wave representing the binary baseband data. The FSK modulated signal is then up-converted to a higher frequency for transmission over a wireless link. This implementation has the advantage of being simple, however, suffers from the frequency drift of the free-running VCO.
In another implementation, the VCO is made part of a frequency synthesizer Phase Locked Loop (PLL), as shown in FIG. 2. The FSK modulator 20 of FIG. 2 includes a crystal oscillator 22, Phase/Frequency Detector Change Pump (PFD/CP) 24, a low pass filter 26, a VCO 28 and a dual-modulus divider (N/N+1) 30. The FSK modulator 20 produces a high stability VCO frequency and reduces its frequency drift over time. Further, in this configuration, the PLL is designed so that the VCO nominal frequency is set to the desired transmit frequency of the transmitter. No up-conversion is required. The VCO nominal frequency is synthesized from the crystal oscillator 22 through the PLL. To introduce the FSK modulation, the dual-modulus divider 30 is used in the PLL loop. The baseband data bits of “1”s and “0”s select one of the two divide values of the dual-modulus divider 30. This implementation is referred to as direct VCO modulation. The main advantage of this implementation is the complete elimination of the image problem that is found in all Superhetrodyne and Low-IF transmitter architectures (i.e., that results whenever up-conversion of the modulated signal to a higher frequency is required). However, it imposes major constraints on the PLL loop design and the data rate that can be transmitted. Therefore, it requires significant amount of design efforts to ensure proper operation.
The above methods for generating FSK modulation are of analog nature. An all-digital implementation is advantageous for many reasons. First, it lends itself well for integration with baseband digital processors and requires smaller die area. Another significant advantage is that an all-digital implementation allows early verification of the modulator performance both in a software modeling environment as well as in hardware. For example, during design, the performance in an analog-like implementation (i.e., direct VCO modulation) can only be verified in the analog design and simulation environment. No testing or verification using hardware is possible until the chip is fabricated. However, with an all-digital implementation, it is possible to generate a hardware description for the actual design (i.e., Register Transfer Level: RTL), and test and verify the design on a Field Programmable Gate Array (FPGA) chip. This significantly reduces the risk and provides an early opportunity to capture errors or improve the design before taping out the chip. Such errors or design improvements may only be discovered in an analog-like implementation after the chip is manufactured, requiring another costly tape out.
In its simplest form, an all-digital FSK modulator requires a reference clock and a divider with two divide values. The reference clock is divided by one divide value when the data bit is “1”, and is divided by the other divide value when the data bit is “0”. The output of the dividing operation is a pulse waveform. Typically, a D flip-flop is used at the output to generate a square wave that is FSK modulated. FIG. 3 illustrates an FSK modulation by using the reference clock. In FIG. 3, “A0” represents the reference clock; “B0” represents a data bit; “C0” represents divide values; “D0” represents the resulting binary FSK modulated square wave. For M-ary FSK modulation, multiple divide values result in an M-ary FSK modulated square waveform. As shown in FIG. 3, an instantaneous frequency change in the resulting FSK modulated signal occurs using this implementation
U.S. Pat. No. 5,712,878 (Nemer) discloses a digital FSK modulator that implements the above operation via a state machine. Although higher order FSK modulation is possible, the frequency of the resulting FSK modulated signal is changed almost instantly. This instantaneous frequency change causes higher sidebands in the FSK modulated signal spectrum and results in the FSK modulated signal occupying wider bandwidth. This may be acceptable for some systems. However, when operating a wireless device in most of the frequency bands, regulations require the signal not to occupy more than a specified bandwidth and the sidebands be lower than a specified level.
In U.S. Pat. No. 3,890,581 (Stuart et al.) and U.S. Pat. No. 3,997,855 (Nash), the frequency is changed through a sequence of frequency steps when the data changes from one state to the other. This essentially results in a smoother frequency transition and results in lower spectral sidebands. In U.S. Pat. No. 3,890,581, the intermediate frequency steps are achieved by generating an internal variable duty-cycle sequence that is used to progressively increase or decrease the frequency of the modulated signal. In U.S. Pat. No. 3,997,885, an Up-Down counter is used to produce the intermediate frequency steps.
FIG. 4 illustrates conventional FSK modulation with intermediate frequency steps. As shown in FIG. 4, when the data bit changes, the frequency is stepped up or down starting from the middle of the current bit to the middle of the following bit.
Another desired feature of any modulator is to be able to design a single modulator architecture that is able to operate and produce several modulation schemes with little or no added complexity. This allows one to design a single modulator that can be used in various applications and many frequency bands with little or no effort. However, this should not make such a modulator complex as this translates into higher power consumption. Therefore there is a need to design a modulator that is capable of multi-format modulation, and consumes negligible power compared to a single format modulator.
Very often, modulation is produced at low frequency for easy implementation. This produces a modulated signal centered around a low carrier frequency, often called intermediate frequency or IF. Before transmission, the IF modulated signal must be up-converted to the actual transmission frequency using up-conversion mixers. Such process suffers from a well known problem called image problem. The image problem occurs when a single mixer is used to up-convert the modulated signal. The mixer mixes the modulated (i.e. desired) signal with a local signal (LO signal), coming from a local oscillator. By selecting the proper frequency of the LO signal, the output of the mixer includes the modulated signal at the right transmission frequency. However, by nature of the mixer operation, the up-converted signal will also contain an image of the modulated IF signal. The image is located at a frequency that is distant from the desired carrier frequency. The separation is equal to twice the IF frequency. Hence, in such architectures, a band pass filter is required to filter out the image.
FIG. 5 is a diagram illustrating an IQ front-end transmitter architecture for image rejection. Referring to FIG. 5, a well-known architecture that solves the image problem is the IQ architecture, where the signal is formatted into an In-phase (I) and Quadrature (Q) components (42, 44 and 46). Then each component is mixed with a locally generated LO signal (48, 50) and the output is summed (52). In this architecture, the IQ Generation block 42 takes in the IF modulated signal and generates the I and Q signals. The I signal is simply the IF modulated signal unchanged, while the Q signal is a signal generated by phase shifting the I signal by 90°.
Several techniques are deployed to produce the 90° phase shift. One known technique is to use analog delay cells to generate the 90° phase shift. This technique suffers from requiring a large number of delay cells especially when the IF frequency is low. This results in large die area. Further, since it relies on analog delay cells, it suffers from supply, temperature and process variations. This results in part to part variation in terms of how much image rejection is provided. A better technique that is suited to digital implementations is to generate the IF modulated signal at twice the desired IF frequency and then divide the generated modulated signal (at 2×fIF) by two. The divide by two operation allows one to generate a modulated signal at the IF frequency and another copy that is 90° phase shifted. The advantage of this technique is its simplicity and guaranteed 90° phase shift. The disadvantage is that it requires the modulator to run at double the clock that is required to generate the IF modulated signal. Doubling the frequency of such a clock increases power consumption.